2 Remote English-speaking jobs in Feldkirchen in Kärnten

Digital Verification Engineer responsible for developing and maintaining block/subsystem verification environments. Duties include executing plans, managing regressions, creating testbenches, and driving verification closure using SystemVerilog, UVM, and Cadence Xcelium.

Seeking an experienced Digital Designer/RTL Design Engineer to support low-power, multi-clock-domain digital block design and development. Responsibilities include RTL development in VHDL/System Verilog, optimization, and integration.